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Mobilint NPU architecture

Mobilint NPU architecture

Mobilint NPU architecture

Mobilint designs the NPU architecture, compiler, quantizer and runtime together, so one architecture runs CNNs, LLMs and multimodal models efficiently and scales from a single core to a full server.

Why edge NPUs fall short on modern AI.

Why edge NPUs fall short on modern AI.

Why edge NPUs fall short on modern AI.

Workload fragmentation

Workload fragmentation

CNNs, LLMs and multimodal models use different compute patterns. One design rarely runs them all efficiently.

Activation function cost

Activation function cost

GELU and SiLU are expensive to build directly in hardware.

Precision trade-off

Precision trade-off

Lower precision saves memory but costs accuracy. Higher precision costs power and area.

Our Approach: Hardware and Software Co-optimization.

Our Approach: Hardware and Software Co-optimization.

Our Approach: Hardware and Software Co-optimization.

HW/SW co-design

HW/SW co-design

Hardware and compiler are designed together, so one chip runs CNNs, LLMs and multimodal models efficiently.

LUT-based nonlinear functions

LUT-based nonlinear functions

GELU and SiLU run on lookup tables at minimal cost, and complex functions stay accurate.

Mixed-precision quantization engine

Mixed-precision quantization engine

Analyzes data distributions and sets the right precision for each layer automatically, cutting memory traffic to up to 75% without losing accuracy.

Linearly scales from
Core → Cluster → Chip → System.

Linearly scales from
Core → Cluster → Chip → System.

Linearly scales from
Core → Cluster → Chip → System.

Throughput scales almost linearly from one to eight cores, and one programming model covers every level.

System

Chip #1

Cluster #1

Core

Core #2

Core #3

Core #4

Cluster #2

Cluster #3

Cluster #4

Chip #2

Chip #3

Chip #4

01 · CORE

NPU Core

The smallest building block of the Mobilint NPU. Each core is configurable from 1 to 10 TOPS.

02 · CLUSTER

Multi-Core

Up to eight cores share on-chip memory inside a cluster, so they can split one model or run several in parallel. ARIES groups 4 cores with 16 MiB per cluster.

03 · CHIP

Multi-Cluster

Clusters tile across the die to scale compute on one chip. ARIES combines 2 clusters, 8 cores and 80 TOPS in a single chip.

04 · SYSTEM

Multi-Chip

Chips scale out across a board for larger workloads, as on the MLA400 PCIe card, with one programming model at every level.

01 · CORE

NPU Core

NPU Core

1–40 TOPS | ARIES: 10 TOPS

The smallest building block of the Mobilint NPU. Each core is configurable from 1 to 10 TOPS.

02 · CLUSTER

Multi-Core

Multi-Core

1–8 Cores | ARIES: 4 Cores

Up to eight cores share on-chip memory inside a cluster, so they can split one model or run several in parallel. ARIES groups 4 cores with 16 MiB per cluster.

03 · CHIP

Multi-Cluster

Multi-Cluster

1–8 Clusters | ARIES: 2 Clusters

Clusters tile across the die to scale compute on one chip. ARIES combines 2 clusters, 8 cores and 80 TOPS in a single chip.

04 · SYSTEM

Multi-Chip

Multi-Chip

1–n Chips

Chips scale out across a board for larger workloads, as on the MLA400 PCIe card, with one programming model at every level.

Inside every cluster.

Inside every cluster.

Inside every cluster.

Each cluster pairs three specialized engines with a shared scratchpad memory (SPM). Data moves between engines on-chip, so off-chip memory access stays to a minimum.

Cluster + Shared SPM

Cluster + Shared SPM

Shared data within the cluster → minimal off-chip access

TCE

TCE

TCE

Tensor Compute Engine

Tensor Compute Engine

Matrix multiplication for CNN and LLM workloads

TME

TME

TME

Tensor Memory Engine

Tensor Memory Engine

DMA, data movement and buffer management

VCE

VCE

VCE

Vector Compute Engine

Vector Compute Engine

LUT-based activations and vector operations

What the architecture delivers.

What the architecture delivers.

What the architecture delivers.

Efficiency that holds as you scale

Efficiency that holds as you scale

Performance rises almost linearly as cores are added, with higher throughput than competing designs in the same silicon area.

One unified programming model

One unified programming model

The same code runs at full performance from compact devices to servers, with no recompiling.

Quantization that keeps accuracy

Quantization that keeps accuracy

Mobilint’s mixed-precision engine sets precision layer by layer automatically, preserving model quality.

Mixed precision quantization

Mixed precision quantization

Mixed precision quantization

The qb Compiler sets precision in three levels.

Supported weights: 1, 2, 3, 4 and 8-bit. Activations: 8 and 16-bit. Values are restored to full precision inside the chip as they’re read, so smaller weights mean less memory traffic.

Layer

Layer

Each layer gets its own precision.

Group

Group

Precision is set per group of values within a layer.

Element

Element

Outliers stay in high precision while the rest compress. Unevenly spread values use lookup-table quantization.

75%

75%

75%

Up to 75% less memory traffic.

99%+

99%+

99%+

Over 99% of FP16 accuracy retained, with no retraining.

From graph to instruction in five stages.

Optimization narrows step by step, from the network graph to tiles, layers, instructions and weights. Each stage builds on the previous result and converges on a single MXQ file.

01 Network Optimization

network_opt

Graph-level optimization: operator fusion and equivalent rewrites that fit the NPU’s constraints.

Graph level
EQUIVALENT PATTERNOp AOp BOp C

02 Tile Optimization

tile_opt

Finds NPU-optimal block sizes, weighing compute and memory efficiency together.

Block level
LAYER

03 Layer Optimization

layer_opt

Builds on the tiling result to optimize memory. Data moves from DDR to on-chip memory once and is reused there.

Layer + memory
DDROn-chipload × 1load × 1feedfeedSAMSPMCompute CoresreuseSPM reuse × N · on-chip only

04 Instruction Generation

network_to_inst

Generates optimized NPU instructions, then optimizes again at the instruction level.

Instruction level
# layer L12 · tile[0..3] (fused conv+bias+relu)LOADw.cmem ← ddr[W12]LOADx.dmem ← ddr[X12.t0]CONVy.dmem = x.dmem @ w.cmemBIASy.dmem += b.cmemACTy.dmem = relu(y.dmem)STOREddr[Y12.t0] ← y.dmem# scheduler: LOAD/COMPUTE overlap ✓

05 Weight Conversion

weight_to_npu_weight

Converts weights to the execution format and memory layout the NPU expects.

Weight level
Trained layoutblkblkblkblkblkblk

An MXQ executable that runs on any Mobilint NPU.

From graph to instruction in five stages.

Optimization narrows step by step, from the network graph to tiles, layers, instructions and weights. Each stage builds on the previous result and converges on a single MXQ file.

01 Network Optimization

network_opt

Graph-level optimization: operator fusion and equivalent rewrites that fit the NPU’s constraints.

Graph level
EQUIVALENT PATTERNOp AOp BOp C

02 Tile Optimization

tile_opt

Finds NPU-optimal block sizes, weighing compute and memory efficiency together.

Block level
LAYER

03 Layer Optimization

layer_opt

Builds on the tiling result to optimize memory. Data moves from DDR to on-chip memory once and is reused there.

Layer + memory
DDROn-chipload × 1load × 1feedfeedSAMSPMCompute CoresreuseSPM reuse × N · on-chip only

04 Instruction Generation

network_to_inst

Generates optimized NPU instructions, then optimizes again at the instruction level.

Instruction level
# layer L12 · tile[0..3] (fused conv+bias+relu)LOADw.cmem ← ddr[W12]LOADx.dmem ← ddr[X12.t0]CONVy.dmem = x.dmem @ w.cmemBIASy.dmem += b.cmemACTy.dmem = relu(y.dmem)STOREddr[Y12.t0] ← y.dmem# scheduler: LOAD/COMPUTE overlap ✓

05 Weight Conversion

weight_to_npu_weight

Converts weights to the execution format and memory layout the NPU expects.

Weight level
Trained layoutblkblkblkblkblkblk

An MXQ executable that runs on any Mobilint NPU.